1. Field of the Invention
The invention relates to a packaging for holding both microprocessors and memory chips, which increases data access speed and minimizes timing skews by arranging the microprocessors and their associated memories in close proximity to one another.
2. Description of the Related Art
Microprocessors and memory chips are an essential part of almost every computer today. The speed at which a computer performs operations is partially dependent on the speed at which information is transferred between its microprocessor and the memory. There is an ever-increasing need for faster operating computers. By decreasing the time it takes for a microprocessor to access data contained within the memory units, the operating speed of the computer can be increased.
Microprocessors and memories operate in what is called a master-slave relationship. That is, the microprocessor essentially directs the memory operation. This is accomplished through a common bus which connects the microprocessor to the memory. The bus is nothing more than a collection of lines which connect to both the memory and the microprocessor. When a computer seeks to read information from, or write information to, the memory, the address of the particular memory location or locations is placed on the bus and transmitted to the memory. Then, if the microprocessor is reading from the memory, the information stored in the selected locations is transmitted over the bus lines to the microprocessor. If the microprocessor is writing to the memory, information travels from the microprocessor and is stored in the selected memory location(s).
Various types of memories are used in today""s computers. Dynamic Random Access Memories (DRAMs) store information dynamically in the form of a stored charge on a capacitor. Since the charge stored on the capacitor has a tendency to leak away over time, the charge must be constantly refreshed. DRAM technology is conventional in the art and is explained in U.S. Pat. No. 4,081,701 to White Jr. et al., which is herein incorporated by reference. DRAMs are beneficial because they provide more input/output (I/O) paths than standard memory devices. Static Random Access Memories (SRAMs) are another type of memory device. SRAMs store information by latching a set of transistors into one of two states, indicative of the associated logic level (i.e., a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). Unlike DRAMs, it is not necessary to refresh SRAMs since condition of the memory location is represented by a transistor state, rather than charge stored on a capacitor. SRAM technology is also conventional in the art, and is shown in U.S. Pat. No. 4,653,025 to Minato et al., which is herein incorporated by reference. Both DRAMs and SRAMs provide high data transfer rates, and both are widely used in the art.
Data transmission speeds would be greatly increased if both memory and microprocessors could be packaged on a single chip. The proximity of the circuits limits the travel time of the signals, and increases efficiency. Recently, a xe2x80x9cSystem Modulexe2x80x9d has been developed which consists of a logic and memory chip stacked on top of one another with their contacts facing each other. This technique has been described, for example, by Yamaguchi et al. in xe2x80x9cSystem module: a new Chip-On-Chip module technologyxe2x80x9d, Proceedings of IEEE 1997 Custom Integrated Circuit Conference, p.439-442, 1997, which is herein incorporated by reference.
The xe2x80x9cSystem Modulexe2x80x9d is formed by pressing two separate chips 10, 20 (i.e. logic and memory, respectively) together and bonding them, as shown in FIGS. 1A and 1B. FIG. 1A shows the chips prior to be being pressed together. The chips are attached with their contacts 30, 40 facing each other. The connection is formed by placing solder balls 50 on the contact points of the chips, pressing the chips together, and reheating the solder so that it sets. FIG. 1B shows the chips after they have been pressed and heated. This concept is referred to as xe2x80x9cmicro bumpxe2x80x9d or xe2x80x9cflip chipxe2x80x9d bonding. FIGS. 1A and 1B show solder balls on the contacts of both chips, however, it is only required that one chip have solder balls placed on its contacts. In the xe2x80x9cSystem Modulexe2x80x9d, the xe2x80x98busxe2x80x99 which exchanges information between the logic chip and the memory is actually the solder bump connections. Once the xe2x80x9cSystem Modulexe2x80x9d has been fabricated, it is placed in a lead frame, or other suitable device, for connection to other devices. The xe2x80x9cSystem Modulexe2x80x9d provides for high data transfer rates because the logic (10) and the memory (20) chips are in direct contact with very little signal propagation distance therebetween. The disadvantage of this device is that only two chips at a time may be connected in this manner. Further, there is no room for placement of auxiliary circuits, such as active and passive devices which can be used to enhance the performance of the logic and memory circuits.
Although the xe2x80x9cSystem Modulexe2x80x9d provides a short connection line between the two connected IC chips, it does not allow for the connection of additional circuits. In addition, in order to connect more than one memory and logic circuit together at a time, or to connect auxiliary circuits to the logic circuit or memory, longer connection lines (buses) are needed. Longer connection lines allow more circuits to be connected, but also increase the overall size of the device. Further, long lines cause signal delays and timing skews as explained below.
A major problem which occurs in many microprocessor/memory systems is timing skew. Since vast amounts of data are being transmitted over a bus at any one time, clock signals are used to synchronize various circuits which retrieve or transmit data. Timing skew occurs when respective clock signals, for synchronizing different circuits, do not reach their destination at approximately the same time. Timing skew is usually not a problem in devices which have short data paths and short clock paths, because the respective clock signals often reach their destination at the same time. However, as the length of these lines increases, clock speed must be reduced to compensate for the signal delay caused by the longer data lines. When memory and logic circuits are connected using longer bus lines, timing skew becomes a serious problem, especially at high clock rates.
Many prior art schemes have been developed to deal with timing skew problems. One solution is to use a phase locked loop circuit to synchronize the clock signals. Phase locked loop circuits are often utilized to synchronize clock signals on a chip with clock signals off-chip. A main clock generator determines the rate at which data is being transmitted or received by the computer. Since the main clock generator is usually not placed on the chip, it must travel a certain distance to reach the chip. This inherently means that the clock signal is experiencing some type of delay due to the length it travels. Once the main clock signal reaches the chip it must be synchronized with the on-chip clock generator. The phase locked loop circuit locks on to the off-chip clock and synchronizes it with the clock generator on-chip. This synchronization eliminates timing skew problems which occur due to the length of different clock lines.
There is currently a need for a microchip-memory interconnection system which allows many chips to be connected at once, and which does not suffer from timing skew problems. By connecting together multiple chips through relatively short bus lines, and by using auxiliary circuits, such as phase locked loop circuits, to minimize timing skews, an increase in data transmission rates can be easily achieved.
The present invention provides a superior method of packaging microprocessors and memory chips on a common silicon chip to form a multi-chip module.
The invention provides a silicon interposer chip package which is capable of carrying multiple IC chips and which does not suffer timing skew problems. This is accomplished by making the interconnection lines between the IC chips relatively short. The invention also provides active and passive circuits within the interposer substrate. These active and passive circuits increase the overall efficiency of the device. The invention also reduces timing skews which occur outside the interposer by utilizing an active circuit, such as a phase locked loop circuit, placed within the interposer substrate.
The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiment which is provided in connection with the accompanying drawings.